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advanced product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs43l41 low power 24-bit, 96 khz dac with volume control features l complete stereo dac system: interpolation, d/a, output analog filtering l atapi mixing l 101 db dynamic range l 89 dbfs thd+n l low clock jitter sensitivity l +2.4 v to +5 v power supply l filtered line level outputs l on-chip digital de-emphasis for 32, 44.1, and 48 khz l digital volume control with soft ramp C 94 db attenuation C 1 db step size C zero crossing click-free transitions l 24 mw with 2.4 v supply description the cs43l41 is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture and a high tolerance to clock jitter. the cs43l41 accepts data at audio sample rates from 2 khz to 100 khz, consumes very little power and oper- ates over a wide power supply range. these features are ideal for portable dvd, portable mp3, mini-disc, and mobile phones. ordering information CS43L41-KZ 16-pin tssop, -10 to 70 c i volume control interpolation filter ds dac analog filter control port volume control interpolation filter analog filter serial port scl/cclk mutec ad0/cs aouta aoutb rst lrck sdata mclk sda/cdin ds dac external mute control sclk mixer 2 sep 99 ds473pp1
cs43l41 2 ds473pp1 table of contents 1. characteristics and specifications ........................................................................ 5 analog characteristics ................................................................................................ 5 power and thermal characteristics....................................................................... 7 digital characteristics ................................................................................................. 7 absolute maximum ratings ........................................................................................... 7 recommended operating conditions ....................................................................... 7 switching characteristics .......................................................................................... 8 switching characteristics - control port......................................................... 10 2. typical connection diagram .................................................................................... 11 3. register quick reference .......................................................................................... 14 3.1 mclk control (address 00h) ............................................................................................ 14 3.2 mode control (address 01h) ............................................................................................. 14 3.3 volume and mixing control (address 02h)........................................................................ 15 3.4 channel a volume control (address 03h) ........................................................................ 15 3.5 channel b volume control (address 04h) ........................................................................ 15 4. register bit description .............................................................................................. 16 4.1 master clock divide enable.............................................................................................. 16 4.2 auto-mute .................................................................................................................. ....... 16 4.3 digital interface format................................................................................................... .. 17 4.4 de-emphasis control ........................................................................................................ 17 4.5 power on/off quiescent voltage ramp ........................................................................... 18 4.6 power down................................................................................................................. ..... 18 4.7 channel a volume = channel b volume.......................................................................... 19 4.8 soft ramp or zero cross enable...................................................................................... 19 4.9 atapi channel mixing and muting ................................................................................... 20 4.10 mute ...................................................................................................................... .......... 21 4.11 volume control ............................................................................................................ ... 22 5. pin description ........................................................................................................... ...... 23 analog power - va.............................................................................................................. .... 23 analog ground - agnd .......................................................................................................... 2 3 analog output - aouta and aoutb ..................................................................................... 23 reference ground - ref_gnd .............................................................................................. 23 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ i 2 c is a registered trademark of philips semiconductors. spi is a registered trademark of international business machines corporation. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs43l41 ds473pp1 3 confidential draft 9/23/99 positive voltage reference - filt+........................................................................................ 22 quiescent voltage - vq ......................................................................................................... .22 master clock - mclk ............................................................................................................ .23 left/right clock - lrck ........................................................................................................ .23 serial audio data - sdata .................................................................................................... 23 serial clock - sclk ............................................................................................................ .... 24 reset - rst .................................................................................................................... ........ 24 serial control interface clock - scl/cclk ........................................................................... 24 serial control data i/o - sda/cdin ....................................................................................... 24 address bit / chip select - ad0/cs ........................................................................................ 24 mute control - mutec ........................................................................................................... 24 6. applications .............................................................................................................. ....... 25 6.1 grounding and power supply decoupling ....................................................................... 25 6.2 oversampling modes ....................................................................................................... 2 5 6.3 recommended power-up sequence ............................................................................... 25 6.4 use of the power on/off quiescent voltage ramp ..................................................... 25 7. control port interface .............................................................................................. 26 7.1 spi mode .................................................................................................................. ....... 26 7.2 i 2 c compatible mode ...................................................................................................... 26 7.3 memory address pointer (map) ....................................................................................... 27 8. parameter definitions .................................................................................................. 33 total harmonic distortion + noise (thd+n) .......................................................................... 33 dynamic range .................................................................................................................. .... 33 interchannel isolation ......................................................................................................... .... 33 interchannel gain mismatch ................................................................................................... 33 gain error ..................................................................................................................... .......... 33 gain drift ..................................................................................................................... ........... 33 9. references ................................................................................................................ ........ 33 10. package dimensions .................................................................................................... 34
cs43l41 4 ds473pp1 list of figures figure 1. external serial mode input timing ................................................................................. 9 figure 2. internal serial mode input timing .................................................................................. 9 figure 3. internal serial clock generation .................................................................................... 9 figure 4. i 2 c control port timing ................................................................................................ 10 figure 5. spi control port timing .............................................................................................. .12 figure 6. typical connection diagram ........................................................................................ 13 figure 7. spi mode control port formatting ............................................................................... 28 figure 8. i 2 c mode control port formatting ................................................................................ 28 figure 9. base-rate stopband rejection .................................................................................... 29 figure 10. base-rate transition band .......................................................................................... 2 9 figure 11. base-rate transition band (detail) ............................................................................. 29 figure 12. base-rate passband ripple ........................................................................................ 29 figure 13. high-rate stopband rejection ..................................................................................... 29 figure 14. high-rate transition band ........................................................................................... 29 figure 15. high-rate transition band (detail) .............................................................................. 30 figure 16. high-rate passband ripple ......................................................................................... 30 figure 17. output test load .................................................................................................... ..... 30 figure 18. maximum loading ..................................................................................................... ... 30 figure 19. power vs. sample rate (va = 5v) ............................................................................... 30 figure 20. cs43l41 format 0 (i 2 s) .............................................................................................. 31 figure 21. cs43l41 format 1 (i 2 s) .............................................................................................. 31 figure 22. cs43l41 format 2 .................................................................................................... ... 31 figure 23. cs43l41 format 3 .................................................................................................... ... 32 figure 24. cs43l41 format 4 .................................................................................................... ... 32 figure 25. cs43l41 format 5 .................................................................................................... ... 32 figure 26. cs43l41 format 6 .................................................................................................... ... 33 figure 27. de-emphasis curve ................................................................................................... .. 33 figure 28. atapi block diagram ................................................................................................. .33 list of tables table 1. master clock divide enable ............................................................................................ ... 16 table 2. auto-mute enable...................................................................................................... ......... 16 table 3. digital interface formats ............................................................................................. ....... 17 table 4. de-emphasis filter configurations ..................................................................................... 17 table 5. power on/off ramp enable .............................................................................................. .18 table 6. power down enable ..................................................................................................... ...... 18 table 7. a=b volume control enable............................................................................................. .. 19 table 8. soft ramp and zero cross enable..................................................................................... 20 table 9. atapi decode.......................................................................................................... .......... 20 table 10. mute enable .......................................................................................................... ........... 21 table 11. digital volume settings .............................................................................................. ...... 22 table 12. common clock frequencies ............................................................................................ 2 4
cs43l41 ds473pp1 5 1. characteristics and specifications analog characteristics (t a = 25 c; logic "1" = va; logic "0" = agnd; full-scale output sine wave, 997 hz; mclk = 12.288 mhz; fs for base-rate mode = 48 khz, sclk = 3.072 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified; fs for high-rate mode = 96 khz, sclk = 6.144 mhz, measurement bandwidth 10 hz to 40 khz, unless otherwise specified. test load r l = 10 k w, c l = 10 pf (see figure 17)), notes: 1. one-half lsb of triangular pdf dither is added to data. parameter base-rate mode high-rate mode symbol min typ max min typ max unit dynamic performance for va = 5 v specified temperature range t a -10 - 70 -10 - 70 c dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 92 96 - - 97 101 95 99 - - - - 91 95 - - 96 100 94 98 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -89 -77 -37 -88 -75 -35 -84 -72 -32 - - - - - - - - - -89 -74 -36 -89 -73 -34 -84 -69 -31 - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db dynamic performance for va = 2.4 v specified temperature range t a -10 - 70 -10 - 70 c dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 92 95 91 94 - - - - tbd tbd - - 91 95 90 94 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -91 -72 -32 -90 -71 -31 tbd tbd tbd - - - - - - - - - -89 -71 -31 -88 -70 -30 tbd tbd tbd - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db
cs43l41 6 ds473pp1 analog characteristics (continued) notes: 2. refer to figure 18. 3. filter response is guaranteed by design. 4. response is clock dependent and will scale with fs. note that the response plots (figures 9-16) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 5. for base-rate mode, the measurement bandwidth is 0.5465 fs to 3 fs. for high-rate mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 6. de-emphasis is not available in high-rate mode. parameters symbol min typ max units analog output full scale output voltage 0.63?va 0.7?va 0.77?va vpp quiescent voltage v q -0.5?va- vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c ac-load resistance (note 2) r l 3- -k w load capacitance (note 2) c l --100pf parameter base-rate mode high-rate mode symbol min typ max min typ max unit combined digital and on-chip analog filter response (note 3) passband (note 4) to -0.05 db corner to -0.1 db corner to -3 db corner 0 - 0 - - - .4535 - .4998 - 0 0 - - - - .4621 .4982 fs fs fs frequency response 10 hz to 20 khz -.02 - +.08 -0.06 - 0 db stopband .5465 - - .577 - - fs stopband attenuation (note 5) 50 - - 55 - - db group delay tgd - 9/fs - - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - - 0.36/fs - - - - 1.39/fs 0.23/fs - - s s de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - +.2/-.1 +.05/-.14 +0/-.22 (note 6) db db db
cs43l41 ds473pp1 7 power and thermal characteristics notes: 7. refer to figure 19. 8. valid with the recommended capacitor values on filt+ and v q as shown in figure 1. digital characteristics (t a = 25 c; va = 2.28v - 5.5v) absolute maximum ratings (agnd = 0v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd = 0v; all voltages with respect to ground.) parameters symbol min typ max units power supplies power supply current normal operation va = 5 v power-down state i a i a - - 15 60 17 - ma m a power dissipation (note 7) va = 5 v normal operation power-down - - 75 0.3 85 - mw mw power supply current normal operation va = 2.4 v power-down state i a i a - - 10 30 tbd - ma m a power dissipation (note 7) va = 2.4 v normal operation power-down - - 24 0.07 tbd - mw mw package thermal resistance q ja -110-c/watt power supply rejection ratio (1 khz) (note 8) (60 hz) psrr - - 60 40 - - db db parameters symbol min typ max units high-level input voltage va = 5 v va = 2.4 v v ih 2.0 2.0 - - - - v v low-level input voltage va = 5 v va = 2.4 v v il - - - - 0.8 0.8 v v input leakage current i in --10 m a input capacitance - 8 - pf maximum mutec drive current - 3 - ma parameters symbol min max units dc power supply va -0.3 6.0 v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 va+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units dc power supply va 2.28 5.0 5.5 v
cs43l41 8 ds473pp1 switching characteristics (t a = -10 to 70 c; va = 2.4v - 5.5v; inputs: logic 0 = 0v, logic 1 = va, c l = 20pf) notes: 9. in internal sclk mode, the duty cycle must be 50% 1/2 mclk period. 10. the sclk / lrck ratio may be either 32, 48, or 64. this ratio depends on part type and mclk/lrck ratio. (see figures 20-26) parameters symbol min typ max units input sample rate fs 2 - 100 khz mclk pulse width high mclk/lrck = 512 10 - 1000 ns mclk pulse width low mclk/lrck = 512 10 - 1000 ns mclk pulse width high mclk / lrck = 384 or 192 21 - 1000 ns mclk pulse width low mclk / lrck = 384 or 192 21 - 1000 ns mclk pulse width high mclk / lrck = 256 or 128 31 - 1000 ns mclk pulse width low mclk / lrck = 256 or 128 31 - 1000 ns external sclk mode lrck duty cycle (external sclk only) 40 50 60 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period mclk / lrck = 512, 256 or 384 t sclkw -- ns sclk period mclk / lrck = 128 or 192 t sclkw -- ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns internal sclk mode lrck duty cycle (internal sclk only) (note 9) - 50 - % sclk period (note 10) t sclkw -- ns sclk rising to lrck edge t sclkr -- m s sdata valid to sclk rising setup time t sdlrs -- ns sclk rising to sdata hold time mclk / lrck = 512, 256 or 128 t sdh -- ns sclk rising to sdata hold time mclk / lrck = 384 or 192 t sdh -- ns 1 128 () fs --------------------- - 1 64 () fs ------------------ 1 sclk ---------------- tsclkw 2 ----------------- - 1 512 () fs --------------------- -10 + 1 512 () fs --------------------- -15 + 1 384 () fs --------------------- -15 +
cs43l41 ds473pp1 9 sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. external serial mode input timing sdata *internal sclk lrck sclkw t sdlrs t sdh t sclkr t figure 2. internal serial mode input timing *the sclk pulses shown are internal to the cs43l41. sdata lrck mclk *internal sclk 1 n 2 n figure 3. internal serial clock generation * the sclk pulses shown are internal to the cs43l41. n equals mclk divided by sclk
cs43l41 10 ds473pp1 switching characteristics - control port (t a = 25 c; va = +5 v 5%; inputs: logic 0 = agnd, logic 1 = va, c l = 30 pf) notes: 11. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c ? compatible mode scl clock frequency f scl -100khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 11) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of both sda and scl lines t r -1s fall time of both sda and scl lines t f -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 4. i 2 c control port timing
cs43l41 ds473pp1 11 switching characteristics - control port (t a = 25 c; va = +5 v 5%; inputs: logic 0 = agnd, logic 1 = va, c l = 30 pf) notes: 12. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 13. data must be held for sufficient time to bridge the transition time of cclk. 14. for f sck < 1 mhz parameter symbol min max unit spi ? mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 12) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 13) t dh 15 - ns rise time of cclk and cdin (note 14) t r2 -100ns fall time of cclk and cdin (note 14) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 5. spi control port timing
cs43l41 12 ds473pp1 2. typical connection diagram 13 audio data processor external clock mclk agnd aoutb cs4341 sdata lrck va aouta 3 4 5 14 0.1 f + 1f 12 +5 v to + 2.4 v 3.3 f 3.3 f 10 k w c c 560 w 560 w + + - controlled configuration 8 6 7 sclk 1 2 scl/cclk sda/cdin ad0/cs rst mutec 16 optional mute circuit 15 1f 0.1 f audio output a audio output b r l r l + + 10 k w .1 f 1f 9 10 11 ref_gnd filt+ vq c= 4 p fs(r 560) l r560 l + figure 6. typical connection diagram
cs43l41 ds473pp1 13 3. register quick reference ** default ==> bit status after power-up-sequence or reset. 3.1 mclk control (address 00h) mclkdiv (mclk divide-by-2 enable) default = 0. 0 - disabled 1 - enabled 3.2 mode control (address 01h) amute (auto-mute) default = 1. 0 - disabled 1 - enabled dif2, dif1 and dif0 (digital interface format) default = 0. 0 - format 0, i 2 s, up to 24-bit data, 64 x fs internal sclk 1 - format 1, i 2 s, up to 24-bit data, 32 x fs internal sclk 2 - format 2, left justified, up to 24-bit data 3 - format 3, right justified, 24-bit data 4 - format 4, right justified, 20-bit data 5 - format 5, right justified, 16-bit data 6 - format 6, right justified, 18-bit data 7 - identical to format 1 dem 1, dem 0 (de-emphasis mode) default = 0. 0 - disabled 1 - 44.1 khz de-emphasis 2 - 48 khz de-emphasis 3 - 32 khz de-emphasis por (power on/off quiescent voltage ramp) default = 1. 0 - disabled 1 - enabled pdn (power-down) default =1. 0 - disabled 1 - enabled 76543210 reserved reserved reserved reserved reserved reserved mclkdiv reserved 00000000 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn 10000011
cs43l41 14 ds473pp1 3.3 volume and mixing control (address 02h) a = b (channel a volume = channel b volume) default = 0. 0 - aouta volume is determined by register 03h and aoutb volume is determined by register 04h. 1 - aouta and aoutb volumes are determined by register 03h and register 04h is ignored. soft & zero cross (soft control and zero cross detection control) default = 10. soft zero cross mode 0 0 changes take effect immediately 0 1 changes take effect on zero crossings 1 0 changes take effect with a soft ramp (default) 1 1 changes take effect in 1/8 db steps on each zero crossing atapi 0-4 (channel mixing and muting) (refer to table 9) default = 01001, (stereo) aouta = left channel aoutb = right channel 3.4 channel a volume control (address 03h) 3.5 channel b volume control (address 04h) mute default = 0 0 - disabled 1 - enabled volume default = 0 (refer to table 11) 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 01001001 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 00000000
cs43l41 ds473pp1 15 4. register bit description 4.1 master clock divide enable mclk control register (address 00h) access: r/w in i 2 c and write only in spi. default: 0 - disabled function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2. note: this feature is present on revision c and newer devices. for backward compatibility with pre- vious revision devices, this bit defaults to zero. 4.2 auto-mute mode control register (address 01h) access: r/w in i 2 c and write only in spi. default: 1 - enabled function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-zero data will release the mute. detection and mut- ing is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is effected, similar to volume control changes, by the soft and zero cross bits in the volume and mixing control register. 76543210 reserved reserved reserved reserved reserved reserved mclkdiv reserved mclkdiv mode 0 disabled 1 enabled table 1. master clock divide enable 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn amute mode 0 disabled 1 enabled table 2. auto-mute enable
cs43l41 16 ds473pp1 4.3 digital interface format mode control register (address 01h) access: r/w in i 2 c and write only in spi. default: 0 - format 0 (i 2 s, up to 24-bit data, 64 x fs internal sclk) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 20-26. 4.4 de-emphasis control mode control register (address 01h) access: r/w in i 2 c and write only in spi. default: 0 - disabled function: implementation of the standard 15 m s/50 m s digital de-emphasis filter response, figure 27, requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. note: de-emphasis is not available in high-rate mode. 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn dif2 dif1 dif0 description format figure 000 i 2 s, up to 24-bit data, 64 x fs internal sclk 020 001 i 2 s, up to 24-bit data, 32 x fs internal sclk 121 0 1 0 left justified, up to 24-bit data 2 22 0 1 1 right justified, 24-bit data 3 23 1 0 0 right justified, 20-bit data 4 24 1 0 1 right justified, 16-bit data 5 25 1 1 0 right justified, 18-bit data 6 26 1 1 1 identical to format 1 7 20 table 3. digital interface formats 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn dem1 demo description 0 0 disabled 0144.1khz 1048khz 1132khz table 4. de-emphasis filter configurations
cs43l41 ds473pp1 17 4.5 power on/off quiescent voltage ramp mode control register (address 01h) access: r/w in i 2 c and write only in spi. default: 1 - enabled function: the power on/off quiescent voltage ramp allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off. please refer to the applications section for details of implementing this feature. 4.6 power down mode control register (address 01h) access: r/w in i 2 c and write only in spi. default: 1 - enabled function: the device will enter a low-power state whenever this function is activated. the power-down bit de- faults to enabled on power-up and must be disabled before normal operation will begin. the contents of the control registers are retained in this mode. 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn por mode 0 disabled 1 enabled table 5. power on/off ramp enable 76543210 amute dif2 dif1 dif0 dem1 dem0 por pdn pdn mode 0 disabled 1 enabled table 6. power down enable
cs43l41 18 ds473pp1 4.7 channel a volume = channel b volume volume and mixing control register (address 02h) access: r/w in i 2 c and write only in spi. default: 0 - disabled function: the aouta and aoutb volume levels are independently controlled by the a and the b channel vol- ume control bytes when this function is disabled. the volume on both aouta and aoutb are de- termined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 4.8 soft ramp or zero cross enable volume and mixing control register (address 02h) access: r/w in i 2 c and write only in spi. default: 10 - soft ramp enabled. function: soft ramp enable soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1db per 8 left/right clock periods. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 a = b mode 0 disabled 1 enabled table 7. a=b volume control enable 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0
cs43l41 ds473pp1 19 soft ramp and zero cross enable soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 4.9 atapi channel mixing and muting volume and mixing control register (address 02h) access: r/w in i 2 c and write only in spi. default: 01001 - aouta=al, aoutb=br (stereo) function: the cs43l41 implements the channel mixing functions of the atapi cd-rom specification. refer to table 9 and figure 28 for additional information. soft zero mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled table 8. soft ramp and zero cross enable 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 01111 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br table 9. atapi decode
cs43l41 20 ds473pp1 4.10 mute channel a volume control register (address 03h) channel b volume control register (address 04h) access: r/w in i 2 c and write only in spi. default: 0 - disabled function: the digital-to-analog converter output will mute when enabled. the quiescent voltage on the output will be retained. the muting function is effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. the mutec will go active during the mute pe- riod if the mute function is enabled for both channels. 10010 mute bl 10011 mute [(al+br)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(bl+ar)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 11111 [(al+br)/2] [(al+br)/2] 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 mute mode 0 disabled 1 enabled table 10. mute enable atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb table 9. atapi decode (continued)
cs43l41 ds473pp1 21 4.11 volume control channel a volume control register (address 03h) channel b volume control register (address 04h) access: r/w in i 2 c and write only in spi. default: 0 - 0 db (no attenuation) function: the digital volume control allows the user to attenuate the signal in 1 db increments from 0 to -90 db. volume settings are decoded as shown in table 11. the volume changes are implemented as dic- tated by the soft and zero cross bits in the volume and mixing control register. all volume settings less than - 94 db are equivalent to enabling the mute bit. 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 11. digital volume settings
cs43l41 22 ds473pp1 5. pin description analog power - va pin 14, input function: analog power supply. typically 2.4 to 5vdc. analog ground - agnd pin 13, input function: analog ground reference. analog output - aouta and aoutb pins 12 and 15, output function: the full scale analog output level is specified in the analog characteristics specifications table. reference ground - ref_gnd pin 11, input function: ground reference for the internal sampling circuits. must be connected to analog ground. positive voltage reference - filt+ pin 9, output function: positive reference for internal sampling circuits. external capacitors are required from filt+ to analog ground, as shown in figure 6. the recommended values will typically provide 60 db of psrr at 1 khz and 40 db of psrr at 60 hz. filt+ is not intended to supply external current. filt+ has a typical source impedance of 250 k w and any current drawn from this pin will alter device performance. quiescent voltage - vq pin 10, output function: filter connection for internal quiescent reference voltage, typically 50% of va. capacitors must be con- nected from v q to analog ground, as shown in figure 6. v q is not intended to supply external current. v q has a typical source impedance of 250 k w and any current drawn from this pin will alter device perfor- mance. 15 2 14 3 13 4 16 1 11 6 10 7 9 8 12 5 reset rst mutec mute control serial data sdata aouta analog output a serial clock sclk va analog power left/right clock lrck agnd analog ground master clock mclk aoutb analog output b scl/cclk scl/cclk ref_gnd reference ground sda/cdin sda/cdin vq quiescent voltage ad0/cs ad0/cs filt+ positive voltage reference
cs43l41 ds473pp1 23 master clock - mclk pin 5, input function: the master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in base rate mode (brm) and 128x, 192x, 256x or 384x the input sample rate in high rate mode (hrm). note that some multiplication factors require setting the mclkdiv bit in the mclk control register. table 12 illustrates several standard audio sample rates and the required master clock frequencies. left/right clock - lrck pin 4, input function: the left/right clock determines which channel is currently being input on the serial audio data input, sda- ta. the frequency of the left/right clock must be at the input sample rate. audio samples in left/right sample pairs will be simultaneously output from the digital-to-analog converter whereas right/left pairs will exhibit a one sample period difference. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte and the options are detailed in figures 20-26. serial audio data - sdata pin 2, input function: two's complement msb-first serial data is input on this pin. the data is clocked into sdata via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte and the options are de- tailed in figures 20-26. sample rate (khz) mclk (mhz) hrm brm 128x 192x 256x* 384x* 256x 384x 512x 768x* 1024x* 32 4.0960 6.1440 8.1920 12.2880 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 5.6448 8.4672 11.2896 16.9344 11.2896 16.9344 22.5792 32.7680 45.1584 48 6.1440 9.2160 12.2880 18.4320 12.2880 18.4320 24.5760 36.8640 49.1520 64 8.1920 12.2880 16.3840 24.5760 - - - - - 88.2 11.2896 16.9344 22.5792 33.8688 - - - - - 96 12.2880 18.4320 24.5760 36.8640 - - - - - * requires mclkdiv bit = 1 in mclk control register (address 00h) table 12. common clock frequencies
cs43l41 24 ds473pp1 serial clock - sclk pin 3, input function: clocks the individual bits of the serial data into the sdata pin. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte and the options are de- tailed in figures 20-26. the cs43l41 supports both internal and external serial clock generation modes. the internal serial clock mode eliminates possible clock interference from an external sclk. use of the internal serial clock mode is always preferred. internal serial clock mode in the internal serial clock mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. the sclk/lrck frequency ratio is either 32, 48, or 64 depending upon data format, as shown in figures 20-26. operation in this mode is identical to operation with an external serial clock synchronized with lrck. external serial clock mode the cs43l41 will enter the external serial clock mode whenever 16 low to high transitions are detected on the sclk pin during any phase of the lrck period. the device will revert to internal serial clock mode if no low to high transitions are detected on the sclk pin for 2 consecutive periods of lrck. reset - rst pin 1, input function: the device enters a low power mode and all internal registers are reset to the default settings, including the control port, when low. when high, the control port becomes operational and the pdn bit must be cleared before normal operation will occur. the control port can not be accessed when reset is low. serial control interface clock - scl/cclk pin 6, input function: clocks the serial control data into or from sda/cdin. serial control data i/o - sda/cdin pin 7, input/output function: in i 2 c mode, sda is a data i/o line. cdin is the input data line for the control port interface in spi mode. address bit / chip select - ad0/cs pin 8, input function: in i 2 c mode, ad0 is a chip address bit. cs is used to enable the control port interface in spi mode. the device will enter the spi mode at anytime a high to low transition is detected on this pin. once the device has entered the spi mode, it will remain until either the part is reset or undergoes a power-down cycle. mute control - mutec pin 16, output function: the mute control pin goes high during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. this pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. use of mute control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.
cs43l41 ds473pp1 25 6. applications 6.1 grounding and power supply decoupling as with any high resolution converter, the cs43l41 requires careful attention to power sup- ply and grounding arrangements to optimize per- formance. figure 6 shows the recommended power arrangement with va connected to a clean supply. decoupling capacitors should be located as close to the device package as possible. 6.2 oversampling modes the cs43l41 operates in one of two oversampling modes based on the input sample rate and the state of the mclkdiv bit in the mclk control regis- ter. base rate mode (brm) supports input sample rates up to 50 khz while high rate mode (hrm) supports input sample rates up to 100 khz. when the mclkdiv bit is cleared, the devices operate in brm when mclk/lrck is 256, 384 or 512 and in hrm when mclk/lrck is 128 or 192. when the mclkdiv bit is set, the devices operate in brm when mclk/lrck is 512, 768 or 1024 and in hrm when mclk/lrck is 256 or 384. 6.3 recommended power-up sequence 1. hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and v q will remain low. 2. bring rst high. the device will remain in a low power state with v q low and the control port acces- sible. the desired register settings can be loaded while keeping the pdn bit set to 1. 3. set the pdn bit to 0 which will initiate the pow- er-up sequence, which requires approximately 50 s when the por bit is set to 0. if the por bit is set to 1, see section 6.4 for total power-up timing. 6.4 use of the power on/off quiescent voltage ramp the cs43l41 uses a novel technique to minimize the effects of output transients during power-up and power-down. this technique, when used with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients com- monly produced by single-ended single-supply converters. when the device is initially powered-up, the audio outputs, aouta and aoutb, are clamped to agnd. following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. approximately 10,000 left/right clock cycles later, the outputs reach vq and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitor to charge to the quiescent voltage, mini- mizing the power-up transient. to prevent transients at power-down, the device must first enter its power-down state. when this oc- curs, audio output ceases and the internal output buffers are disconnected from aouta and aoutb. in their place, a soft-start current sink is substituted which allows the dc-blocking capaci- tors to slowly discharge. once this charge is dissi- pated, the power to the device may be turned off and the system is ready for the next power-on. to prevent an audio transient at the next power-on, it is necessary to ensure that the dc-blocking ca- pacitors have fully discharged before turning off the power or exiting the power-down state. if not, a transient will occur when the audio outputs are ini- tially clamped to agnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance. for ex- ample, with a 3.3 f capacitor, the minimum pow- er-down time will be approximately 0.4 seconds. use of the mute control function is recommended for designs requiring the absolute minimum in ex- traneous clicks and pops. also, use of the mute
cs43l41 26 ds473pp1 control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. 7. control port interface the control port is used to load all the internal set- tings of the cs43l41. the operation of the control port may be completely asynchronous to the audio sample rate. however, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. * the control port has 2 modes: spi and i 2 c compat- ible, with the cs43l41 operating as a slave device in both modes. if i 2 c operation is desired, ad0/cs should be tied to va or agnd. if the cs43l41 ever detects a high to low transition on ad0/cs af- ter power-up, spi mode will be selected. the con- trol port registers are write-only in spi mode. 7.1 spi mode in spi mode, cs is the cs43l41 chip select signal, cclk is the control port bit clock, cdin is the in- put data line from the microcontroller and the chip address is 0010000. all signals are inputs and data is clocked in on the rising edge of cclk. figure 7 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into the register designated by the map. the cs43l41 has map auto increment capability, enabled by the incr bit in the map register. if incr is 0, then the map will stay constant for suc- cessive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of successive registers. 7.2 i 2 c compatible mode in i 2 c compatible mode, sda is a bi-directional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 8. there is no cs pin. pin ad0 forms the partial chip address and should be tied to va or agnd as required. the upper 6 bits of the 7-bit address field must be 001000. to communi- cate with the cs43l41 the lsb of the chip address field, which is the first byte sent to the cs43l41, should match the setting of the ad0 pin. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then followed by the data to be written. if the operation is a read, then the contents of the reg- ister pointed to by the map will be output after the chip address. the cs43l41 has map auto increment capability, enabled by the incr bit in the map register. if incr is 0, then the map will stay constant for suc- cessive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of successive registers. for more information on i 2 c, please see the i 2 c- bus specification: version 2.0, listed in the ref- erences section. * the mclk is required for both control port inter- faces.
cs43l41 ds473pp1 27 confidential draft 9/23/99 7.3 memory address pointer (map) incr (auto map increment enable) default = 0. 0 - disabled 1 - enabled map0-2 (memory address pointer) default = 000. 76543210 incr reserved reserved reserved reserved map2 map1 map0 00000000 map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 7. spi mode control port formatting sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. i 2 c mode control port formatting
cs43l41 28 ds473pp1 figure 9. base-rate stopband rejection figure 10. base-rate transition band figure 11. base-rate transition band (detail) figure 12. base-rate passband ripple figure 13. high-rate stopband rejection figure 14. high-rate transition band
cs43l41 ds473pp1 29 figure 15. high-rate transition band (detail) figure 16. high-rate passband ripple aoutx agnd 3.3 f v out r l c l + figure 17. output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k w ) l 125 3 20 figure 18. maximum loading 75 50 30 power (mw) sample rate (khz) br m h r m 70 65 60 55 40 50 60 70 80 90 100 figure 19. power vs. sample rate (va = 5v)
cs43l41 30 ds473pp1 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, up to 24-bit data and int sclk = 64 fs if mclk/lrck = 512, 256 or 128i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 384 or 192 i 2 s, up to 24-bit datadata valid on rising edge of sclk figure 20. cs43l41 format 0 (i 2 s) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, 16-bit data and int sclk = 32 fs if mclk/lrck = 512, 256 or 128i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 384 or 192 i 2 s, up to 24-bit datadata valid on rising edge of sclk figure 21. cs43l41 format 1 (i 2 s) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode left justified, up to 24-bit dataint sclk = 64 fs if mclk/lrck = 512, 256 or 128int sclk = 48 fs if mclk/lrck = 384 or 192 left justified, up to 24-bit datadata valid on rising edge of sclk figure 22. cs43l41 format 2
cs43l41 ds473pp1 31 lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel internal sclk mode external sclk mode right justified, 24-bit dataint sclk = 64 fs if mclk/lrck = 512, 256 or 128int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 24-bit datadata valid on rising edge of sclksclk must have at least 48 cycles per lrck period figure 23. cs43l41 format 3 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 internal sclk mode external sclk mode right justified, 20-bit dataint sclk = 64 fs if mclk/lrck = 512, 256 or 128int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 20-bit datadata valid on rising edge of sclksclk must have at least 40 cycles per lrck period figure 24. cs43l41 format 4 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks internal sclk mode external sclk mode right justified, 16-bit dataint sclk = 32 fs if mclk/lrck = 512, 256 or 128int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 16-bit datadata valid on rising edge of sclksclk must have at least 32 cycles per lrck period figure 25. cs43l41 format 5
cs43l41 32 ds473pp1 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks internal sclk mode external sclk mode right justified, 18-bit dataint sclk = 64 fs if mclk/lrck = 512, 256 or 128int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 18-bit datadata valid on rising edge of sclksclk must have at least 36 cycles per lrck period figure 26. cs43l41 format 6 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 27. de-emphasis curve ss a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 28. atapi block diagram
cs43l41 ds473pp1 33 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1) how to achieve optimum performance from delta-sigma a/d & d/a converters by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2) cdb43l41 evaluation board datasheet 3) the i 2 c bus specification: version 2.0 philips semiconductors, december 1998. http://www.semiconductors.philips.com
cs43l41 34 ds473pp1 10. package dimensions notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.043 -- 1.10 a1 0.002 0.006 0.05 0.15 a2 0.034 0.037 0.85 0.95 b 0.008 0.012 0.19 0.30 2,3 d 0.193 0.201 4.90 5.10 1 e 0.248 0.256 6.30 6.50 e1 0.169 0.177 4.30 4.50 1 e -- 0.026 -- 0.65 l 0.020 0.028 0.50 0.70 0 8 0 8 16l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
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